A NEW APPROACH OF AN ERROR DETECTING AND CORRECTING CIRCUIT BY ARITHMETIC LOGIC BLOCKS

This paper proposes a unique method of an error detection and correction (EDAC) circuit, carried out using arithmetic logic blocks. The modified logic blocks circuit and its auxiliary components are designed with Boolean and block reduction technique, which reduced one logic gate per block. The reduced logic circuits were simulated and designed using MATLAB Simulink, DSCH 2 CAD, and Microwind CAD tools. The modified, 2:1 multiplexer, demultiplexer, comparator, 1-bit adder, ALU, and error correction and detection circuit were simulated using MATLAB and Microwind. The EDAC circuit operates at a speed of 454.676 MHz and a slew rate of -2.00 which indicates excellence in high speed and low-area.

Pembahagi frekuensi berkuasa rendah menggunakan teknik pincang badan ke depan

Aplikasi tanpa wayar seperti telefon selular, radio dua-hala dan wifi telah menggunakan sepenuhnya teknologi penghantar-terima yang terkini. Unit penghantar-terima yang terdiri daripada penghantar dan penerima merupakan unit yang penting di dalam sistem komunikasi tanpa wayar bagi memastikan penghantaran data yang tepat dapat dilaksanakan. Ketepatan ini dikawal oleh satu unit di dalam penghantar-terima, iaitu Gelung Terkunci Fasa (Phase-Locked Loop, PLL). Penghantar-terima berkuasa rendah adalah penting untuk memanjangkan hayat bateri dalam peranti tanpa wayar. Pembahagi frekuensi di dalam PLL merupakan salah satu penyumbang utama kepada pelesapan kuasa. Oleh itu, projek ini adalah bertujuan untuk menghasilkan satu pembahagi frekuensi berkuasa rendah untuk sistem Gelung Terkunci Fasa, iaitu sistem yang sering digunakan sebagai pensistesis frekuensi di dalam pemancar-penerima radio frekuensi (RF). Untuk mencapai sasaran ini, teknik pincang badan ke depan (FBB) digunakan. FBB mengurangkan voltan ambang dengan mengenakan voltan positif di antara simpang sumber dan badan. Teknik ini membolehkan litar beroperasi dengan sumber voltan yang rendah, oleh itu kuasa yang rendah digunakan. Rekabentuk litar dalam kajian ini diimplementasi menggunakan teknologi Silterra 0.13 μm CMOS. Bagi pembahagi frekuensi, topologi jam fasa tunggal benar (True Single Phase-Clock, TSPC) digunakan kerana ia merupakan litar yang mudah dan mempunyai kos fabrikasi yang rendah berbanding topologi yang lain. Keputusan simulasi menunjukkan pembahagi frekuensi CMOS-FBB mampu beroperasi hingga 5.0 GHz daripada 0.8 V voltan sumber dan hanya menggunakan kuasa sebanyak 34.55 nW. Dibandingkan dengan pembahagi frekuensi menggunakan CMOS konvensional, teknik CMOS-FBB Berjaya mengurangkan kuasa sebanyak 99.98%

Identification of Leptospira in water by Fe-Pd-doped polyaniline nanocomposite thin film

Leptospirosis disease was caused by rat urine which contains the genus Leptospira bacteria. In this study, the fabrication of Pd-Fe-doped polyaniline nanocomposite thin films for the determination of the genus Leptospira bacteria thin films has been investigated. Pd-Fe-doped polyaniline nanocomposite thin films were fabricated by sol–gel spin coating method. The electrode sensors were immersed in the Leptospira solution. The resulting materials were investigated using field-emission scanning electron microscopy, atomic force microscopy, transmission electron microscopy, and current–voltage measurement. The atomic force microscopy images show the specific morphology films’ structure for Leptospira detection, whereas the field-emission scanning electron microscopy image shows the irregularity of clump nanoparticles in thin film surfaces. Transmission electron microscopy result shows that metal alloy (Fe-Pd) embedded in the polymer matrix. Current–voltage measurement with and without incubation of the thin film into Leptospira solution was done to show the relationship between concentration bacteria versus current. The result shows that polyaniline-Fe0.4-Pd0.6 nanocomposite thin film has higher sensitivity in detecting Leptospira, where it has performed with the highest percentage of the sensitivity of 16.9%. Besides that, selectivity tests were conducted to distinguish the existence of Leptospira, Pseudomonas aeruginosa, and Staphylococcus aureus bacteria. These results confirm the potentials of polyaniline metal alloys’ nanocomposite thin films to be used for Leptospira bacteria detection in water

Reference spurs in an integer-N phase-locked loop : analysis, modelling and design.

The Phase-Locked Loop (PLL) is commonly used for frequency synthesis in RF transceivers. It can be implemented in two architectures, namely, fractional-N and integer- N. In this thesis, the integer-N architecture is chosen due to its suitability for frequency planning. Here, a PLL with a low noise output is important to ensure signal purity. There are two dominant noise sources in a PLL, namely, phase noise and periodic noise. In the integer-N PLL, periodic noise is also referred to as a reference spur, where the noise gives rise to multiple reference frequency offsets at the PLL output. Of these two noise sources, this thesis is focused on the analysis and suppression of reference spurs. It is because less work has been carried in the literature regarding spurs, and phase noise is better studied. The main factors underlying reference spurs are discussed. These factors are mainly from the charge pump and phase/frequency detector (PFD) circuit non-idealities, namely, PFD delay, charge pump current leakage, charge pump current mismatch, and rise and fall times characteristic of the charge pump current. Reference spur magnitude can be predicted via a transient analysis. The simulation is time consuming, as the reference spur magnitude can only be captured after the PLL in its locked state. Therefore, the simulation period has to be set long enough to ensure enough data can be obtained to read that state. In this thesis, a reference spur mathematical analysis is presented to accurately estimate the reference spur magnitude. In the analysis, all the circuit non-idealities that contribute to the reference spur are considered. Circuit parameters required in the mathematical analysis can be obtained from transistor level simulation for each circuit. As the simulation for each circuit can be carried out separately, a large amount of simulation time can be saved. The proposed mathematical analysis also can be used to determine the major contributing factor to the problem of reference spurs. The reference spur also can be estimated via behavioural modelling simulation. Behavioural modelling of the PLL using Simulink is presented in this thesis. Each PLL component is modelled separately, and circuit non-idealities contributing to the reference spur are included in the behavioural model. In addition to reference spur estimation, the PLL behavioural model also can be used to visualise the dynamic behaviour of the system. Results from the spur analysis show that a slight mismatch current in the charge pump helps to improve the reference spur performance. This thesis presents an analysis to determine an optimum charge pump current ratio for reference spur suppression, which is caused by the charge pump current mismatch and the switching delay. Further, a ratioed current charge pump circuit is proposed to replace the conventional charge pump circuit for a reference spur performance improvement. This spur suppression technique is implemented using a 180 nm SiGe BiCMOS technology for performance evaluation.Thesis (Ph.D. )-- University of Adelaide, School of Electrical and Electronic Engineering, 201

A New Approach of an Error Detecting and Correcting Circuit by Arithmetic Logic Blocks

This paper proposes a unique method of an error detection and correction (EDAC) circuit, carried out using arithmetic logic blocks. The modified logic blocks circuit and its auxiliary components are designed with Boolean and block reduction technique, which reduced one logic gate per block. The reduced logic circuits were simulated and designed using MATLAB Simulink, DSCH 2 CAD, and Microwind CAD tools. The modified, 2:1 multiplexer, demultiplexer, comparator, 1-bit adder, ALU, and error correction and detection circuit were simulated using MATLAB and Microwind. The EDAC circuit operates at a speed of 454.676 MHz and a slew rate of -2.00 which indicates excellence in high speed and low-area

THE DEVELOPMENT OF AN INNOVATIVE SUPERVISION SYSTEM: E-MENTOR MENTEE SYSTEM IN JKEES

The online mentor mentee system or simply known as e-mentor mentee system that is implemented in the Department of Electrical, Electronic and Systems Engineering (JKEES), Faculty of Engineering and Built Environment (DEBE), Universiti Kebangsaan Malaysia (UKM) is considered as a new mechanism used to monitor and observe engineering student’s academic performance throughout their undergraduate studies. This system was developed to store student’s personal information and academic records for every semester. It is first designed intended for mentors to have an easy access to the information stored, to observe, supervise and update mentees latest information. Aligned with the development of this innovative system, JKEES now owned a database system that is systematic, organized and effective in UKM

DESIGN OF A LOW-POWER AND HIGH THROUGHPUT ERROR DETECTION AND CORRECTION CIRCUIT USING THE 4T EX-OR METHOD

This paper describes an efficient implementation of an error correction circuit based on single error detection and correction with check bit pre-computation. The core component of the proposed 4-bit EX-OR circuit was designed using the CMOS cascade method. This paper presents a 4-input EX-OR gate that was developed from a 2-input EX-OR gate using the bit slice method. The proposed architecture retains the modified Error Correction Code (ECC) circuit. The proposed 4-input EX-OR gate and its auxiliary components such as AND, MUX and D Flip-Flop were schematized using the DSCH tool and the layouts was analysed using the BSIM4 analyser. The simulation results were obtained and compared with the performance of existing circuits. LVS verification was performed on the modified ECC circuit at CMOS 70 nm feature size and its corresponding voltage of 0.7V. The modified ECC circuit simulation results were analysed and compared with the performance of existing circuits in terms of propagation delay, power dissipation, area, latency, and throughput. The proposed ECC circuit showed an improved performance with existing circuit low power dissipation (94.41%) and high throughput (95.20%)

Assessment of a 16-Channel Ambulatory Dry Electrode EEG for Remote Monitoring

Ambulatory EEGs began emerging in the healthcare industry over the years, setting a new norm for long-term monitoring services. The present devices in the market are neither meant for remote monitoring due to their technical complexity nor for meeting clinical setting needs in epilepsy patient monitoring. In this paper, we propose an ambulatory EEG device, OptiEEG, that has low setup complexity, for the remote EEG monitoring of epilepsy patients. OptiEEG’s signal quality was compared with a gold standard clinical device, Natus. The experiment between OptiEEG and Natus included three different tests: eye open/close (EOC); hyperventilation (HV); and photic stimulation (PS). Statistical and wavelet analysis of retrieved data were presented when evaluating the performance of OptiEEG. The SNR and PSNR of OptiEEG were slightly lower than Natus, but within an acceptable bound. The standard deviations of MSE for both devices were almost in a similar range for the three tests. The frequency band energy analysis is consistent between the two devices. A rhythmic slowdown of theta and delta was observed in HV, whereas photic driving was observed during PS in both devices. The results validated the performance of OptiEEG as an acceptable EEG device for remote monitoring away from clinical environments